The invention relates, in general, to non-volatile memory devices and, more particularly, to a method of fabricating a non-volatile memory device, in which it can solve problems of a contact etch process for fabricating transistors of a peripheral region.
A non-volatile memory device is a memory device having the property of maintaining data although the supply of power is stopped. The non-volatile memory device includes a charge trap layer in which charges are trapped between the gate of a transistor and a channel in order to implement the difference of threshold voltage (Vth) of the channel. The threshold voltage is varied depending on a state where charges are injected into the charge trap layer, that is, a program state or an erase state where electrons are discharged. An operation of a device is implemented by employing the concept in which the threshold voltage is varied by charges trapped or stored in the charge trap layer as described above.
In a typical flash memory device, a floating gate employing a metal layer or a polysilicon layer has been used as the charge trap layer. Thus, the non-volatile memory device stores information in such a manner that electrons, which have passed through the tunneling layer by applying high voltage to the gate upon program (Pgm), are trapped at a trap site of the floating gate, that is, the charge trap layer. At time of an erase operation for erasing the information stored as described above, the electrons trapped at the floating gate are extracted toward the substrate by means of the Fowler-Nordheim (FN) tunneling method by applying a negative gate voltage −Vg to the gate or grounding the gate, and applying high voltage to the substrate. Meanwhile, recently, research has been done into a flash memory device of a Silicon-Oxide-Nitride-Oxide Silicon (SONOS) structure in which the floating gate is formed from a nitride layer not a metal layer or a polysilicon layer.
However, the flow of unnecessary electrons occurs in a flash memory cell of the SONOS structure at the time of the erase operation. In the concrete, at the time of the program operation, high voltage is applied to the control gate. In this case, there occurs a back tunneling phenomenon in which the electrons of the control gate are injected into the floating gate through the dielectric layer. The back tunneling phenomenon hinders electrons from being completely discharged from the floating gate at the time of the erase operation, degrading an erase characteristic.
In recent years, in order to solve the problem that the erase characteristic is degraded due to the back tunneling phenomenon, an oxide layer formed from high dielectric (h-k) material, such as Al2O3, HfO2, or ZrO2, as the blocking oxide layer, is formed between the control gate and the nitride layer used as the floating gate. Such an oxide layer mitigates an electric field to prevent the back tunneling phenomenon of electrons.
However, in the peripheral region, a gate oxide layer/a first polysilicon layer/a tunneling layer/a trap nitride layer/a blocking oxide layer/a second polysilicon layer have a lamination structure. In order to form a transistor, the oxide layer and the nitride layer between the first polysilicon layer and the second polysilicon layer must be etched in order to electrically connect the first polysilicon layer and the second polysilicon layer.
However, in the case where the blocking oxide layer is formed from high dielectric material, such as Al2O3, HfO2, or ZrO2, it is difficult to etch the blocking oxide layer formed from the high dielectric material by means of the existing dry etch process. Due to this, a contact hole is not formed up to the tunneling layer in a desired fashion. In the worst case, the first polysilicon layer and the second polysilicon layer are not connected, resulting in failure.
To solve the problem that the blocking oxide layer formed from the high dielectric material is not etched, a wet etch process has been introduced instead of the dry etch process. However, the blocking oxide layer formed from the high dielectric material is well etched by the wet etch process, but is isotropically etched at the time of the wet etch process. Thus, the blocking oxide layer, the trap nitride layer and the tunneling layer are over etched, causing loss. It reduces process margin and increases the size of the transistor.